橙盒科技承接、单片机解密、FPGA解密、DSP解密以及其他专用IC及疑难IC的解密项目，CY8C3445LTI-089是CYPRESS系列单片机之一，目前，橙盒科技在CYPRESS系列单片机解密领域已经取得系列突破，可提供多种型号IC及单片机的解密服务，详情请与橙盒科技联系，这里我们仅提供对CY8C3445LTI-089单片机的基本功能特征介绍：
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　　Figure 1-1 illustrates the major components of the CY8C34
　　family. They are:
　　8051 CPU Subsystem
　　Nonvolatile Subsystem
　　Programming, Debug, and Test Subsystem
　　Inputs and Outputs
　　Clocking
　　Power
　　Digital Subsystem
　　Analog Subsystem
　　PSoC’s digital subsystem provides half of its unique configurability.
　　It connects a digital signal from any peripheral to any
　　pin through the Digital System Interconnect (DSI). It also
　　provides functional flexibility through an array of small, fast, low
　　power Universal Digital Blocks (UDBs). PSoC Creator provides
　　a library of pre-built and tested standard digital peripherals
　　(UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR,
　　and so on) that are mapped to the UDB array. The designer can
　　also easily create a digital circuit using boolean primitives by
　　means of graphical design entry. Each UDB contains Programmable
　　Array Logic (PAL)/Programmable Logic Device (PLD)
　　functionality, together with a small state machine engine to
　　support a wide variety of peripherals.
　　In addition to the flexibility of the UDB array, PSoC also provides
　　configurable digital blocks targeted at specific functions. For the
　　CY8C34 family these blocks can include four 16-bit timer,
　　counter, and PWM blocks; I2C slave, master, and multi-master;
　　Full-Speed USB; and Full CAN 2.0b.
　　For more details on the peripherals see the “Example Peripherals”
　　section on page 35 of this data sheet. For information on
　　UDBs, DSI, and other digital blocks, see the “Digital Subsystem”
　　section on page 35 of this data sheet.
　　PSoC’s analog subsystem is the second half of its unique configurability.
　　All analog performance is based on a highly accurate
　　absolute voltage reference with less than 0.9% error over
　　temperature and voltage. The configurable analog subsystem
　　includes:
　　Analog muxes
　　Comparators
　　Voltage references
　　Analog-to-Digital Converter (ADC)
　　Digital-to-Analog Converters (DACs)
　　All GPIO pins can route analog signals into and out of the device
　　using the internal analog bus. This allows the device to interface
　　up to 62 discrete analog signals. The heart of the analog
　　subsystem is a fast, accurate, configurable Delta-Sigma ADC
　　with these features:
　　Less than 100 霽 offset
　　A gain error of 0.2%
　　Integral Non Linearity (INL) less than 1 LSB
　　Differential Non Linearity (DNL) less than 1 LSB
　　Signal-to-noise ratio (SNR) better than 70 dB (Delta-Sigma) in
　　12-bit mode
　　This converter addresses a wide variety of precision analog
　　applications including some of the most demanding sensors.
　　Two high speed voltage or current DACs support 8-bit output
　　signals at update rate of 8 Msps in current DAC (IDAC) and 1
　　Msps in voltage DAC (VDAC). They can be routed out of any
　　GPIO pin. You can create higher resolution voltage PWM DAC
　　outputs using the UDB array. This can be used to create a pulse
　　width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz.
　　The digital DACs in each UDB support PWM, PRS, or
　　delta-sigma algorithms with programmable widths.
　　In addition to the ADC and DACs, the analog subsystem
　　provides multiple:
　　Uncommitted opamps
　　Configurable Switched Capacitor/Continuous Time (SC/CT)
　　blocks. These support:
　　Transimpedance amplifiers
　　Programmable gain amplifiers
　　Mixers
　　Other similar analog components
　　See the “Analog Subsystem” section on page 48 of this data
　　sheet for more details.
　　PSoC’s 8051 CPU subsystem is built around a single cycle
　　pipelined 8051 8-bit processor running at up to 48 MHz. The
　　CPU subsystem includes a programmable nested vector
　　interrupt controller, DMA controller, and RAM. PSoC’s nested
　　vector interrupt controller provides low latency by allowing the
　　CPU to vector directly to the first address of the interrupt service
　　routine, bypassing the jump instruction required by other architectures.
　　The DMA controller enables peripherals to exchange
　　data without CPU involvement. This allows the CPU to run
　　slower (saving power) or use those CPU cycles to improve the
　　performance of firmware algorithms. The single cycle 8051 CPU
　　runs ten times faster than a standard 8051 processor. The
　　processor speed itself is configurable allowing active power
　　consumption to be tuned for specific applications.PSoC’s nonvolatile subsystem consists of Flash, byte-writeable
　　EEPROM, and nonvolatile configuration options. It provides up
　　to 64 KB of on-chip Flash. The CPU can reprogram individual
　　blocks of Flash, enabling boot loaders. The designer can enable
　　an Error Correcting Code (ECC) for high reliability applications.
　　A powerful and flexible protection model secures the user’s
　　sensitive information, allowing selective memory block locking
　　for read and write protection. Up to 2 KB of byte-writable
　　EEPROM is available on-chip to store application data.
　　Additionally, selected configuration options such as boot speed
　　and pin drive mode are stored in nonvolatile memory. This allows
　　settings to activate immediately after power on reset (POR).
　　The three types of PSoC I/O are extremely flexible. All I/Os have
　　many drive modes that are set at POR. PSoC also provides up
　　to four I/O voltage domains through the Vddio pins. Every GPIO
　　has analog I/O, LCD drive[1], CapSense[4], flexible interrupt
　　generation, slew rate control, and digital I/O capability. The SIOs
　　on PSoC allow Voh to be set independently of Vddio when used
　　as outputs. When SIOs are in input mode they are high
　　impedance. This is true even when the device is not powered or
　　when the pin voltage goes above the supply voltage. This makes
　　the SIO ideally suited for use on an I2C bus where the PSoC may
　　not be powered when other devices on the bus are. The SIO pins
　　also have high current sink capability for applications such as
　　LED drives. The programmable input threshold feature of the
　　SIO can be used to make the SIO function as a general purpose
　　analog comparator. For devices with Full-Speed USB the USB
　　physical interface is also provided (USBIO). When not using
　　USB these pins may also be used for limited digital functionality
　　and device programming. All the features of the PSoC I/Os are
　　covered in detail in the “I/O System and Routing” section on
　　page 29 of this data sheet.
　　The PSoC device incorporates flexible internal clock generators,
　　designed for high stability and factory trimmed for high accuracy.
　　The Internal Main Oscillator (IMO) is the master clock base for
　　the system, and has 1% accuracy at 3 MHz. The IMO can be
　　configured to run from 3 MHz up to 45 MHz. Multiple clock derivatives
　　can be generated from the main clock frequency to meet
　　application needs. The device provides a PLL to generate
　　system clock frequencies up to 48 MHz from the IMO, external
　　crystal, or external reference clock. It also contains a separate,
　　very low power Internal Low Speed Oscillator (ILO) for the sleep
　　and watchdog timers. A 32.768 kHz external watch crystal is also
　　supported for use in Real Time Clock (RTC) applications. The
　　clocks, together with programmable clock dividers, provide the
　　flexibility to integrate most timing requirements.
　　The CY8C34 family supports a wide supply operating range from
　　1.71 to 5.5V. This allows operation from regulated supplies such
　　as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0V ± 10%, or directly
　　from a wide range of battery types. In addition, it provides an
　　integrated high efficiency synchronous boost converter that can
　　power the device from supply voltages as low as 0.5V. This
　　enables the device to be powered directly from a single battery
　　or solar cell. In addition, the designer can use the boost converter
　　to generate other voltages required by the device, such as a 3.3V
　　supply for LCD glass drive. The boost’s output is available on the
　　Vboost pin, allowing other devices in the application to be
　　powered from the PSoC.
　　PSoC supports a wide range of low power modes. These include
　　a 200 nA hibernate mode with RAM retention and a 1 霢 sleep
　　mode with real time clock (RTC). In the second mode the
　　optional 32.768 kHz watch crystal runs continuously and
　　maintains an accurate RTC.
　　Power to all major functional blocks, including the programmable
　　digital and analog peripherals, can be controlled independently
　　by firmware. This allows low power background processing
　　when some peripherals are not in use. This, in turn, provides a
　　total device current of only 1.2 mA when the CPU is running at 6
　　MHz or 0.8 mA running at 3 MHz.
　　The details of the PSoC power modes are covered in the “Power
　　System” section on page 25 of this data sheet.
　　PSoC uses JTAG (4 wire) or Serial Wire Debug (SWD) (2 wire)
　　interfaces for programming, debug, and test. The 1-wire Single
　　Wire Viewer (SWV) may also be used for “printf” style debugging.
　　By combining SWD and SWV, the designer can implement a full
　　debugging interface with just three pins. Using these standard
　　interfaces enables the designer to debug or program the PSoC
　　with a variety of hardware solutions from Cypress or third party
　　vendors. PSoC supports on-chip break points and 4 KB
　　instruction and data race memory for debug. Details of the
　　programming, test, and debugging interfaces are discussed in
　　the “Programming, Debug Interfaces, Resources” section on
　　page 57 of this data sheet.
　　2. Pinouts
　　The Vddio pin that supplies a particular set of pins is indicated
　　by the black lines drawn on the pinout diagrams in Figure 2-1
　　through Figure 2-4. Using the Vddio pins, a single PSoC can
　　support multiple interface voltage levels, eliminating the need for
　　off-chip level shifters. Each Vddio may sink up to 100 mA total to
　　its associated I/O pins and opamps. On the 68 pin and 100 pin
　　devices each set of Vddio associated pins may sink up to 100
　　mA. The 48 pin device may sink up to 100 mA total for all Vddio0
　　plus Vddio2 associated I/O pins and 100 mA total for all Vddio1
　　plus Vddio3 associated I/O pins.