试验环境　FPGA：ep1c6q24c08　　FLASH:am29lv160d

1.擦除

//红色飓风读写，擦除试验,调通2009.12.3.swordjoe

module flash(clk,rst,,busy,oe,ce,we,erase_over,addr,data,data_out,boma,key,seg,sl,buzz,ram_ce,bw,ledd,state);

input clk;
input rst;
input busy;//RY/BY 0正在擦除或编程写入，1表示准备读
input boma;
input key;

output [20:0]addr;
output [15:0]data;

output [15:0]data_out;
output erase_over;
output oe;
output ce;
output we;
output bw;//字节，字使能
output [7:0]seg;
output [3:0]sl;
output buzz;
output ram_ce;//RAM片选
output ledd;
output [5:0]state;
//wire erase_over;

//output write_over;
reg [15:0]data,data_out,data_w,data_du,disp_dat;
//reg erase_over;
reg [20:0]addr,addr_w,addr_du;
reg [7:0]seg_reg;
reg [3:0]sl_reg;
reg [25:0]count;
//reg [23:0]state;
reg [5:0]state;

reg ce,we,oe;
reg ledd;
//reg busy_reg;
//reg write_over;

parameter s1 =6'd0,//24'b0000_0000_0000_0000_0000_0000,
          s2 =6'd1,//24'b0000_0000_0000_0000_0000_0001,
          s3 =6'd2,//24'b0000_0000_0000_0000_0000_0010,
          s4 =6'd3,//24'b0000_0000_0000_0000_0000_0100,
          s5 =6'd4,//24'b0000_0000_0000_0000_0000_1000,
          s6 =6'd5,//24'b0000_0000_0000_0000_0001_0000,
          s7 =6'd6,//24'b0000_0000_0000_0000_0010_0000,
          s8 =6'd7,//24'b0000_0000_0000_0000_0100_0000,
          s9 =6'd8,//24'b0000_0000_0000_0000_1000_0000,
          s10=6'd9,//24'b0000_0000_0000_0001_0000_0000,
          s11=6'd10,//24'b0000_0000_0000_0010_0000_0000,
          s12=6'd11,//24'b0000_0000_0000_0100_0000_0000,
          s13=6'd12,//24'b0000_0000_0000_1000_0000_0000,
          s14=6'd13,//24'b0000_0000_0001_0000_0000_0000,
          s15=6'd14,//24'b0000_0000_0010_0000_0000_0000,
          s16=6'd15,//24'b0000_0000_0100_0000_0000_0000,
          s17=6'd16,//24'b0000_0000_1000_0000_0000_0000,
          s18=6'd17,//24'b0000_0001_0000_0000_0000_0000,
          s19=6'd18,//24'b0000_0010_0000_0000_0000_0000,
          s20=6'd19,//24'b0000_0100_0000_0000_0000_0000,
          s21=6'd20,//24'b0000_1000_0000_0000_0000_0000,
          s22=6'd21,//24'b0001_0000_0000_0000_0000_0000,
          s23=6'd22,//24'b0010_0000_0000_0000_0000_0000,
          s24=6'd23,//24'b0100_0000_0000_0000_0000_0000,
          s25=6'd24;//24'b1000_0000_0000_0000_0000_0000;

count[0])
begin
if(!rst)
begin
state<=s1;
ce<=1;
we<=1;
oe<=1;
end

else
   begin
case(state)
  
    s1:begin
    addr<=21'h555;//
    ce<=1;
    oe<=1;
    we<=1;
    data=16'haa;
    state<=s2;
    end
    s2:begin
    ce<=0;
    we<=0;
       state<=s3;
    end
    s3:begin     
       state<=s4;
    end
    s4:begin
    ce<=1;
    we<=1;
        state<=s5;
    end

  
  
   s5:begin
    addr<=21'h2aa;//
    ce<=1;
    oe<=1;
    we<=1;
    data=16'h55;
    state<=s6;
    end
    s6:begin
    ce<=0;
    we<=0;
       state<=s7;
    end
    s7:begin     
        state<=s8;
    end
    s8:begin
    ce<=1;
    we<=1;
   
    state<=s9;
    end

  
  
   s9:begin
    addr<=21'h555;
    ce<=1;
    oe<=1;
    we<=1;
    data=16'h80;
    state<=s10;
    end
   s10:begin
    ce<=0;
    we<=0;
    //data=16'h80;
    state<=s11;
    end
    s11:begin    
    //data=16'h80;
    state<=s12;
    end
    s12:begin
    ce<=1;
    we<=1;
    //data<=16'hzz;   
    state<=s13;
    end

   
  
   s13:begin
    addr<=21'h555;
   
    ce<=1;
    oe<=1;
    we<=1;
    data=16'haa;
    state<=s14;
    end
    s14:begin
    ce<=0;
    we<=0;
    
    state<=s15;
    end
    s15:begin     
    
    state<=s16;
    end
    s16:begin
    ce<=1;
    we<=1;
    //data<=16'hzz;   
    state<=s17;
    end

   
  
   s17:begin
    addr<=21'h2aa;//addr_du;
    ce<=1;
    oe<=1;
    we<=1;
    data=16'h55;
    state<=s18;
    end
    s18:begin
    ce<=0;
    we<=0;
    
    state<=s19;
    end
    s19:begin     

    state<=s20;
    end
    s20:begin
    ce<=1;
    we<=1;
    //data<=16'hzz;   
    state<=s21;
    end

   
   s21:begin
    addr[20:12]<=9'b000010xxx;//sector erase
    //addr<=21'h555;//chip erase
    ce<=1;
    oe<=1;
    we<=1;
    data=16'h30;//sector erase
    //data=16'h10;//chip erase
    state<=s22;
    end
    s22:begin
    ce<=0;
    we<=0;
  
    state<=s23;
    end
    s23:begin     
   
    state<=s24;
    end
    s24:begin
    ce<=1;
    we<=1;

    ledd<=1;
    state<=s25;
   
    end
   s25:begin
         state<=s25;
         end
   endcase
      end
end

/////////////////////////////////////////////////
/////////////数码管显示//////////////////////////
  
])
begin
   case(count[9:8])
   2'h0:disp_dat<=data[3:0];
   2'h1:disp_dat<=data[7:4];
   2'h2:disp_dat<=data[11:8];
   2'h3:disp_dat<=data[15:12];
   endcase
     
   case(count[9:8])    
   2'h0:sl_reg<=4'b0001;//数码管个位
   2'h1:sl_reg<=4'b0010;
   2'h2:sl_reg<=4'b0100;
   2'h3:sl_reg<=4'b1000;//数码管4位
   endcase    
end

)
begin
case(disp_dat)
    4'h0:seg_reg<=8'hfc;//0红色飓风共阴管   
4'h1:seg_reg<=8'h60;//1
4'h2:seg_reg<=8'hda;//2
4'h3:seg_reg<=8'hf2;//3
4'h4:seg_reg<=8'h66;//4
4'h5:seg_reg<=8'hb6;//5
4'h6:seg_reg<=8'hbe;//6
4'h7:seg_reg<=8'he0;//7
4'h8:seg_reg<=8'hfe;//8
4'h9:seg_reg<=8'hf6;//9
4'ha:seg_reg<=8'hee;//a
4'hb:seg_reg<=8'h3e;//b
4'hc:seg_reg<=8'h9c;//c
4'hd:seg_reg<=8'h7a;//d
4'he:seg_reg<=8'h9e;//e
4'hf:seg_reg<=8'h8e;//f
endcase
end

clk)//计数分频
begin
    count<=count+1;
    //busy_reg<=busy;
end

assign seg=seg_reg;
assign sl=sl_reg;
assign buzz=0;//关掉蜂鸣器
assign ram_ce=1;//关掉RAM片选
assign bw=1;//以字，16位
assign erase_over=busy;
//assign erase_over=busy_reg;
endmodule

2．写入

//红色飓风写,需要19个周期,写入一个数据

module flash(clk,rst,,busy,oe,ce,we,erase_over,addr,data,data_out,boma,key,seg,sl,buzz,ram_ce,bw,ledd);

input clk;
input rst;
input busy;//RY/BY 0正在擦除或编程写入，1表示准备读
input boma;
input key;

output [20:0]addr;
output [15:0]data;

output [15:0]data_out;
output erase_over;//写入完成指示灯
output oe;
output ce;
output we;
output bw;//字节，字使能
output [7:0]seg;
output [3:0]sl;
output buzz;
output ram_ce;//RAM片选
output ledd;//命令写入完指示灯

//wire erase_over;

//output write_over;
reg [15:0]data,data_out,data_w,data_du,disp_dat;
//reg erase_over;
reg [20:0]addr,addr_w,addr_du;
reg [7:0]seg_reg;
reg [3:0]sl_reg;
reg [25:0]count;
reg [15:0]state;
reg ce,we,oe;
reg ledd;
//reg busy_reg;
//reg write_over;

parameter s1 =16'b0000_0000_0000_0000,
          s2 =16'b0000_0000_0000_0001,
          s3 =16'b0000_0000_0000_0010,
          s4 =16'b0000_0000_0000_0100,
          s5 =16'b0000_0000_0000_1000,
          s6 =16'b0000_0000_0001_0000,
          s7 =16'b0000_0000_0010_0000,
          s8 =16'b0000_0000_0100_0000,
          s9 =16'b0000_0000_1000_0000,
          s10=16'b0000_0001_0000_0000,
          s11=16'b0000_0010_0000_0000,
          s12=16'b0000_0100_0000_0000,
          s13=16'b0000_1000_0000_0000,
          s14=16'b0001_0000_0000_0000,
          s15=16'b0010_0000_0000_0000,
          s16=16'b0100_0000_0000_0000,
          s17=16'b1000_0000_0000_0000,
          s18=16'b1000_0000_0000_0001,
          s19=16'b1000_0000_0000_0010,
          s20=16'b1000_0000_0000_0100;
         

initial addr_w=21'h010000;

count[0])
begin
if(!rst)
begin
state<=s1;
ce<=1;
we<=1;
oe<=1;
ledd<=0;
end

else
begin

case(state)

   s1:begin
         addr<=21'h555;//addr_du;        
         ce<=1;
         oe<=1;
         we<=1;
         data=16'haa;//
         state<=s2;
      end
    s2:begin
      ce<=0;
      we<=0;
      state<=s3;
      end
   s3:begin     
          state<=s4;
      end
   s4:begin
      ce<=1;
      we<=1;   
      state<=s5;
      end

   s5:begin
         addr<=21'h2aa;
        
         ce<=1;
         oe<=1;
         we<=1;
         data=16'h55;//data+1;
         state<=s6;
      end
    s6:begin
      ce<=0;
      we<=0;
      state<=s7;
      end
   s7:begin     
           state<=s8;
      end
   s8:begin
      ce<=1;
      we<=1;   
      state<=s9;
      end

   s9:begin
         addr<=21'h555;//addr_du;
        
         ce<=1;
         oe<=1;
         we<=1;
        data=16'ha0;
         state<=s10;
      end
    s10:begin
      ce<=0;
      we<=0;
      state<=s11;
      end
   s11:begin     
      
      state<=s12;
      end
   s12:begin
      ce<=1;
      we<=1;   
      state<=s13;
      end

   s13:begin
             addr<=addr_w;
            
    ce<=1;
    oe<=1;
    we<=1;
    data=addr_w[15:0];
    state<=s14;
        
      end
    s14:begin
      ce<=0;
      we<=0;
      state<=s15;
      end
   s15:begin    
      //data=addr_w[15:0];

      state<=s16;
      end
   s16:begin
      ce<=1;
      we<=1;
      ledd<=1;
      state<=s17;
     
      end

s17:begin//命令写入完后要有一个等待时间（片内执行）
      state<=s19;
         
      end
      s19:begin
      if(addr_w<21'h017fff)
            begin
    if(busy==1)
     begin
     state<=s1;
     addr_w<=addr_w+1'b1;
     end
    else
       state<=s19;
    end
         else
              begin
              addr_w<=21'h010000;
              //ledd<=1;
              state<=s20;
              end
    
      end
   s20:begin
      state<=s20;
    
      end

endcase
end
end

/////////////////////////////////////////////////
/////////////数码管显示//////////////////////////
  
])
begin
   case(count[9:8])
   2'h0:disp_dat<=data[3:0];//4'h1;//data_out[3:0];//
   2'h1:disp_dat<=data[7:4];//4'h2;//data_out[7:4];//
   2'h2:disp_dat<=data[11:8];//4'h3;//data_out[11:8];//
   2'h3:disp_dat<=data[15:12];//4'h4;//data_out[15:12];//
   endcase
     
   case(count[9:8])    
   2'h0:sl_reg<=4'b0001;//数码管个位
   2'h1:sl_reg<=4'b0010;
   2'h2:sl_reg<=4'b0100;
   2'h3:sl_reg<=4'b1000;//数码管4位
   endcase    
end

)
begin
case(disp_dat)
    4'h0:seg_reg<=8'hfc;//0红色飓风共阴管   
4'h1:seg_reg<=8'h60;//1
4'h2:seg_reg<=8'hda;//2
4'h3:seg_reg<=8'hf2;//3
4'h4:seg_reg<=8'h66;//4
4'h5:seg_reg<=8'hb6;//5
4'h6:seg_reg<=8'hbe;//6
4'h7:seg_reg<=8'he0;//7
4'h8:seg_reg<=8'hfe;//8
4'h9:seg_reg<=8'hf6;//9
4'ha:seg_reg<=8'hee;//a
4'hb:seg_reg<=8'h3e;//b
4'hc:seg_reg<=8'h9c;//c
4'hd:seg_reg<=8'h7a;//d
4'he:seg_reg<=8'h9e;//e
4'hf:seg_reg<=8'h8e;//f
endcase
end

clk)//计数分频
begin
    count<=count+1;
    //busy_reg<=busy;
end

assign seg=seg_reg;
assign sl=sl_reg;
assign buzz=0;//关掉蜂鸣器
assign ram_ce=1;//关掉RAM片选
assign bw=1;//以字，16位
assign erase_over=busy;
endmodule

３。读出

//红色飓风读试验,

module flash(clk,rst,,busy,oe,ce,we,erase_over,addr,data,data_out,boma,key,seg,sl,buzz,ram_ce,bw);

input clk;
input rst;
input busy;//RY/BY 0正在擦除或编程写入，1表示准备读
input boma;
input key;

output [20:0]addr;
input [15:0]data;

output [15:0]data_out;
output erase_over;
output oe;
output ce;
output we;
output bw;//字节，字使能
output [7:0]seg;
output [3:0]sl;
output buzz;
output ram_ce;//RAM片选

//wire erase_over;
initial addr_du<=21'h010000;
//output write_over;
reg [15:0]data_out,data_w,data_du,disp_dat;
//reg erase_over;
reg [20:0]addr,addr_w,addr_du;
reg [7:0]seg_reg;
reg [3:0]sl_reg;
reg [25:0]count;
reg [11:0]state;
reg ce,we,oe;
//reg busy_reg;
//reg write_over;

parameter s1 =12'b0000_0000_0000,
          s2 =12'b0000_0000_0001,
          s3 =12'b0000_0000_0010,
          s4 =12'b0000_0000_0100,
          s5 =12'b0000_0000_1000,
          s6 =12'b0000_0001_0000,
          s7 =12'b0000_0010_0000,
          s8 =12'b0000_0100_0000,
          s9 =12'b0000_1000_0000,
          s10=12'b0001_0000_0000,
          s11=12'b0010_0000_0000,
          s12=12'b0100_0000_0000,
          s13=12'b1000_0000_0000;

count[0])
begin
if(!rst)
begin
state<=s1;
ce<=1;
oe<=1;
we<=1;
end
else
begin

case(state)

   s1:begin
         //data<=16'hzzzz;//16'h1234;//
         addr<=addr_du;//addr+1;//21'h1111_abcd;//21'h010021;//
         ce<=1;
         oe<=1;
         we<=1;
         state<=s2;
      end
    s2:begin
      ce<=0;
      oe<=0;
     
      state<=s3;
      end
   s3:begin
      data_out<=data; //data_out+1;//16'h1234;//
      state<=s4;
      end
   s4:begin
     
      ce<=1;
      oe<=1;
     
      state<=s1;
      end
endcase
end
end

oe)
//data_out<=data;
ce)
//data_out<=data;

/////////////////按键控制读地址加///////////////////

count[15])//22正好，按一下增加一个数
begin
if(boma==1)//&&(key==0))
    begin
         if(addr_du<21'h017fff)
            addr_du<=addr_du+1'b1;
          else
            addr_du<=21'h010000;
     end
else
     addr_du<=addr_du;
end

/////////////////////////////////////////////////
/////////////数码管显示//////////////////////////
  
])
begin
   case(count[9:8])
   2'h0:disp_dat<=data_out[3:0];//data[3:0];//4'h1;//
   2'h1:disp_dat<=data_out[7:4];//data[7:4];//4'h2;//
   2'h2:disp_dat<=data_out[11:8];//data[11:8];//4'h3;//
   2'h3:disp_dat<=data_out[15:12];//data[15:12];//4'h4;//
   endcase
     
   case(count[9:8])    
   2'h0:sl_reg<=4'b0001;//数码管个位
   2'h1:sl_reg<=4'b0010;
   2'h2:sl_reg<=4'b0100;
   2'h3:sl_reg<=4'b1000;//数码管4位
   endcase    
end

)
begin
case(disp_dat)
    4'h0:seg_reg<=8'hfc;//0红色飓风共阴管   
4'h1:seg_reg<=8'h60;//1
4'h2:seg_reg<=8'hda;//2
4'h3:seg_reg<=8'hf2;//3
4'h4:seg_reg<=8'h66;//4
4'h5:seg_reg<=8'hb6;//5
4'h6:seg_reg<=8'hbe;//6
4'h7:seg_reg<=8'he0;//7
4'h8:seg_reg<=8'hfe;//8
4'h9:seg_reg<=8'hf6;//9
4'ha:seg_reg<=8'hee;//a
4'hb:seg_reg<=8'h3e;//b
4'hc:seg_reg<=8'h9c;//c
4'hd:seg_reg<=8'h7a;//d
4'he:seg_reg<=8'h9e;//e
4'hf:seg_reg<=8'h8e;//f
endcase
end

clk)//计数分频
begin
    count<=count+1;
    //busy_reg<=busy;
end

assign seg=seg_reg;
assign sl=sl_reg;
assign buzz=0;//关掉蜂鸣器
assign ram_ce=1;//关掉RAM片选
assign bw=1;//以字，16位
assign erase_over=busy;
//assign erase_over=busy_reg;
endmodule