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本帖{zh1}由 mxcai2005 于 2010-4-18 11:41 编辑
GCC 4.5 Release Series
Changes, New Features, and Fixes
Caveats
* GCC now requires the MPC library in order to build. See the prerequisites page for version requirements.
*
Support for a number of older systems and recently unmaintained or untested target ports of GCC has been declared obsolete in GCC 4.5. Unless there is activity to revive them, the next release of GCC will have their sources permanently removed.
The following ports for individual systems on particular architectures have been obsoleted:
o IRIX releases before 6.5 (mips-sgi-irix5*, mips-sgi-irix6.[0-4])
o Solaris 7 (*-*-solaris2.7)
o Tru64 UNIX releases before V5.1 (alpha*-dec-osf4*, alpha-dec-osf5.0*)
o Details for the IRIX, Solaris 7, and Tru64 UNIX obsoletions can be found in the announcement.
* Support has been removed for all the configurations obsoleted in GCC 4.4.
* Support has been removed for the protoize and unprotoize utilities, obsoleted in GCC 4.4.
* Support has been removed for tuning for Itanium1 (Merced) variants. Note that code tuned for Itanium2 should also run correctly on Itanium1.
* GCC now generates unwind info also for epilogues. DWARF debuginfo generated by GCC now uses more features of DWARF3 than it used to do and also some DWARF4 features. GDB older than 7.0 is not able to handle either of these, so to debug GCC 4.5 generated binaries or libraries GDB 7.0 or later is needed. You can disable use of DWARF4 features with -gdwarf-3 -gstrict-dwarf options, or with -gdwarf-2 -gstrict-dwarf restrict GCC to just DWARF2 standard, but epilogue unwind info is emitted unconditionally whenever unwind info is emitted.
* On x86 targets, code containing floating-point calculations may run significantly slower when compiled with GCC 4.5 in strict C99 conformance mode than they did with earlier GCC versions. This is due to stricter standard conformance of the compiler and can be avoided by using the option -fexcess-precision=fast; also see below.
* The function attribute noinline no longer prevents GCC from cloning the function. A new attribute noclone has been introduced for this purpose. Cloning a function means that it is duplicated and the new copy is specialized for certain contexts (for example when a parameter is a known constant).
Java (GCJ)
New Targets and Target Specific Improvements
AIX
* Full cross-toolchain support now available with GNU Binutils
ARM
* GCC now supports the Cortex-M0 and Cortex-A5 processors.
* GCC now supports the ARM v7E-M architecture.
* GCC now supports VFPv4-based FPUs and FPUs with single-precision-only VFP.
* GCC has many improvements to optimization for other ARM processors, including scheduling support for the integer pipeline on Cortex-A9.
* GCC now supports the IEEE 754-2008 half-precision floating-point type, and a variant ARM-specific half-precision type. This type is specified using __fp16, with the layout determined by -mfp16-format. With appropriate -mfpu options, the Cortex-A9 and VFPv4 half-precision instructions will be used.
* GCC now supports the variant of AAPCS that uses VFP registers for parameter passing and return values.
AVR
* The -mno-tablejump option has been removed because it has the same effect as the -fno-jump-tables option.
* Added support for these new AVR devices:
o ATmega8U2
o ATmega16U2
o ATmega32U2
IA-32/x86-64
* GCC now will set the default for -march= based on the configure target.
* GCC now supports handling floating-point excess precision arising from use of the x87 floating-point unit in a way that conforms to ISO C99. This is enabled with -fexcess-precision=standard and with standards conformance options such as -std=c99, and may be disabled using -fexcess-precision=fast.
* Support for the Intel Atom processor is now available through the -march=atom and -mtune=atom options.
* A new -mcrc32 option is now available to enable crc32 intrinsics.
* A new -mmovbe option is now available to enable GCC to use the movbe instruction to implement __builtin_bswap32 and __builtin_bswap64.
* SSE math now can be enabled by default at configure time with the new --with-fpmath=sse option.
* There is a new intrinsic header file, <x86intrin.h>. It should be included before using any IA-32/x86-64 intrinsics.
* Support for the XOP, FMA4, and LWP instruction sets for the AMD Orochi processors are now available with the -mxop, -mfma4, and -mlwp options.
* The -mabm option enables GCC to use the popcnt and lzcnt instructions on AMD processors.
* The -mpopcnt option enables GCC to use the popcnt instructions on both AMD and Intel processors.
M68K/ColdFire
* GCC now supports ColdFire 51xx, 5221x, 5225x, 52274, 52277, 5301x and 5441x devices.
* GCC now supports thread-local storage (TLS) on M68K and ColdFire processors.
MeP
Support has been added for the Toshiba Media embedded Processor (MeP, or mep-elf) embedded target.
MIPS
* GCC now supports MIPS 1004K processors.
* GCC can now be configured with options --with-arch-32, --with-arch-64, --with-tune-32 and --with-tune-64 to control the default optimization separately for 32-bit and 64-bit modes.
* MIPS targets now support an alternative _mcount interface, in which register $12 points to the function's save slot for register $31. This interface is selected by the -mcount-ra-address option; see the documentation for more details.
* GNU/Linux targets can now generate read-only .eh_frame sections. This optimization requires GNU binutils 2.20 or above, and is only available if GCC is configured with a suitable version of binutils.
* GNU/Linux targets can now attach special relocations to indirect calls, so that the linker can turn them into direct jumps or branches. This optimization requires GNU binutils 2.20 or later, and is automatically selected if GCC is configured with an appropriate version of binutils. It can be explicitly enabled or disabled using the -mrelax-pic-calls command-line option.
* GCC now generates more heavily-optimized atomic operations on Octeon processors.
* MIPS targets now support the -fstack-protector option.
* GCC now supports an -msynci option, which specifies that synci is enough to flush the instruction cache, without help from the operating system. GCC uses this information to optimize automatically-generated cache flush operations, such as those used for nested functions in C. There is also a --with-synci configure-time option, which makes -msynci the default.
* GCC supports four new function attributes for interrupt handlers: interrupt, use_shadow_register_set, keep_interrupts_masked and use_debug_exception_return. See the documentation for more details about these attributes. |
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