library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity h31 is port(cp,rst,EN:in std_logic; seg:out std_logic_vector(6 downto 0); op:out std_logic; indata:In Std_Logic_Vector(3 downto 0)); end h31; architecture rtl of h31 is type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9); signal presentstate:state; signal nextstate:state; signal qn:std_logic_vector(3 downto 0); begin switchtonextstate:process(cp,rst,EN) begin If rst='1' Then presentstate<=s0; elsif cp'event and cp='1'then if EN<='0' Then presentstate<=nextstate; else case indata is When"0000"=> presentstate<=s0; When"0001"=> presentstate<=s1; When"0010"=> presentstate<=s2; When"0011"=> presentstate<=s3; When"0100"=> presentstate<=s4; When"0101"=> presentstate<=s5; When"0110"=> presentstate<=s6; When"0111"=> presentstate<=s7; When"1000"=> presentstate<=s8; When"1001"=> presentstate<=s9; When others=> null; end case; end if; end if; end process switchtonextstate; changestatemode:process(presentstate) begin case presentstate is when s0=>nextstate<=s1; qn<="0000"; op<='0'; when s1=>nextstate<=s2; qn<="0001"; op<='0'; when s2=>nextstate<=s3; qn<="0010"; op<='0'; when s3=>nextstate<=s4; qn<="0011"; op<='0'; when s4=>nextstate<=s5; qn<="0100"; op<='0'; when s5=>nextstate<=s6; qn<="0101"; op<='0'; when s6=>nextstate<=s7; qn<="0110"; op<='0'; when s7=>nextstate<=s8; qn<="0111"; op<='0'; when s8=>nextstate<=s9; qn<="1000"; op<='0'; when s9=>nextstate<=s0; qn<="1001"; op<='1'; When others=>null; end case; case qn is When "0000"=>seg<="0111111"; When "0001"=>seg<="0000110"; When "0010"=>seg<="1011011"; When "0011"=>seg<="1001111"; When "0100"=>seg<="1100110"; When "0101"=>seg<="1101101"; When "0110"=>seg<="1111101"; When "0111"=>seg<="0000111"; When "1000"=>seg<="1111111"; When "1001"=>seg<="1101111"; When Others=>NULL; end case; |