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1. Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model. A state machine which uses only Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model. The models selected will influence a design but there are no general indications as to which model is better. Choice of a model depends on the application, execution means (for instance, hardware systems are usually best realized as Moore models) and personal preferences of a designer or programmer.
3. Adv and Disadv: 1).In Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level. 2).All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine, although the converse is not true. 3).Moore machine: the outputs are properties of states themselve, which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output.The outputs are held until you go to some other state. Mealy machine: Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.

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1. Metastability in electronics is the ability of an unstable equilibrium electronic state to persist for an indefinite period in a digital system. Note this definition does not guarantee all of the properties that are sometimes demanded for a metastable state in statistical mechanics. Usually the term is used to describe a state that doesn't settle into a stable '0' or '1' logic level within the time required for proper operation. This can cause the circuit to go into an undefined state and act in unpredictable ways, so it is considered a failure mode in a digital circuit.
2. Metastable states are believed to be inherent features of asynchronous digital systems and systems with more than one clock domain, but careful design can often make the probability of a system failing very small indeed. Metastable states do not occur in fully synchronous systems when the set-up time specifications on logic gates are satisfied.
3. Metastability is an unknown state it is neither Zero nor One.Metastability happens for the design systems violating setup or hole time requirements. Setup time is a requirement , that the data has to be stable before the clock-edge and hold time is a requirement , that the data has to be stable after the clock-edge. The potential violation of the setup and hold violation can happen when the data is purely asynchronous and clocked synchronously.
4. . 1).Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain. Using Synchronizers, recovers from the metastable event 2).Use synchronizers between cross-clocking domains to reduce the possibility from metastability. 3).Using Faster flip-flops (which has narrower Metastable Window).

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1. in synthesis period, I will leave a little margin when I constraint the design and I may over-constraint. if I find setup violation, I will analyze the timing path whether it is normal and modify some constraint in order to let the synthesis tool to optimize the design. I will never concern the hold violation in synthesis period.

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1. Create the clocks ( Frequency, Duty-Cycle). → Clock Constraints
2. Define transition-time requirements for the input-ports → Inout Constraints
3. Specify load values for the output ports → Inout Constraints
4. For the inputs and the outputs, specify the delay values (input delay and ouput delay), which are already consumed by the neighbour chip. → Inout Constraints
5. Specify the case-setting (in case of a mux) to report the timing to a specific paths. → Exception Constraints
6. Specify the False-paths in the design. → Exception Constraints
7. Specify the Multi-cycle paths in the design. → Exception Constraints
8. Specify the clock-uncertainity values (with respect to jitter and the margin values for setup/hold). → Clock Constraints
9. Specify few verilog constructs which are not supported by the synthesis tool.

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1. latch is level sensitive and flip-flop is edge sensitive
2. The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.
3. Power: latch省功耗
4. Area: FF是master-slave结构，面积是latch的两倍
5. Testable: latch is not testable
6. Timing: latch比较Fast，高速电路中基于latch的设计。FF是Glitch Free的，而latch的使能端会引入glitch。Complicated，latch只要考虑D→Q与E→Q的timing arc，而FF则要考虑CLK→Q D→setup D→hold Rst/Set→Removal Recovery

1. In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times.
2. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.
3. Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point.
   Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay buffer so that all clock inputs arrive at the same time

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1. local-skew : In the same clock domain, the difference of timing path insertion delay between two “related” sequential cells.The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.
2. global skew : In the same clock domain, the difference of timing path insertion delay between any two sequential cells.The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.
3. useful skew : the skew can use to increase the performance.Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.