特性

• Rail-to-Rail Input/Output
• Offset: 25µV (typ), 100µV (max)
• Zerø-Drift: 0.35µV/°C (typ), 1.2µV/°C (max)
• Low Noise: 12nV/√Hz
• Input Offset Current: ±5nA max (+25°C)
• Gain Error: 0.1% max (G ≤ 32),
  0.3% max (G > 32)
• Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128(PGA112, PGA116)
• Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
• Gain Switching Time: 200ns
• Two Channel MUX: PGA112, PGA113
  10 Channel MUX: PGA116, PGA117
• Four Internal Calibration Channels
• Amplifier Optimized for Driving CDAC ADCs
• Output Swing: 50mV to Supply Rails
• AV_DD and DV_DD for Mixed Voltage Systems
• I_Q = 1.1mA (typ)
• Software/Hardware Shutdown: I_Q ≤ 4µA (typ)
• Temperature Range: -40°C to +125°C
• SPI Interface (10MHz) with Daisy-Chain Capability
• APPLICATIONS
  • Remote e-Meter Reading
  • Automatic Gain Control
  • Portable Data Acquisition
  • PC-Based Signal Acquisition Systems
  • Test and Measurement
  • Programmable Logic Controllers
  • Battery-Powered Instruments
  • Handheld Test Equipment

SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners

说明

The PGA112 and PGA113 (binary/scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in an MSOP-10 package. The PGA116 and PGA117 (binary/scope gains) offer 10 analog inputs, a four-pin SPI interface with daisy-chain capability, and hardware and software shutdown in a TSSOP-20 package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9V_CAL, 0.1V_CAL, and V_REF, respectively. V_CAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.