可控计数器,是这次课程设计的题目。2周。
设计要求:
1,设计一个五进制的计数器,由三个控制键SEL控制不同的计数方式。
2,当sel=000时,按0,1,2,3,4,0,1,2,3,4…
3,当sel=001时,按0,2,4,6,8,0,2,4,6,8…
4,当sel=010时,按1,3,5,7,9,1,3,5,7,9…
5,当sel=011时,按5,4,3,2,1,5,4,3,2,1…
6,当sel=100时,按 0,1,3,6,9,0,1,3,6,9…
7,当sel=101时,按5,6,7,8,9,5,6,7,8,9…
8,当sel=110时,按2,4,6,8,0,2,4,6,8,0…
9,当sel=110时,按9,8,7,6,5,9,8,7,6,5…
10,由数码管分别译码显示控制信号和计数状态,分别用3位数码管动态显示给出VHDL语言的源程序。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mu is
port(clk,ck:in std_logic;
sel:in std_logic_vector(2 downto 0);
sm:out std_logic_vector(6 downto 0);
duan:out std_logic_vector(5 downto 0));
end mu;
architecture art of mu is
signal cnt:std_logic_vector(3 downto 0);
signal temp:integer range 0 to 5;
signal x:std_logic_vector(7 downto 0);
signal y:std_logic_vector(7 downto 0);
begin
p1:process(clk)
begin
cnt<=”0101″;
else cnt<=cnt+1;
end if;
y<=cnt;
when “110″=>if(cnt=”1000″)then
cnt<=”0000″;
else cnt<=cnt+2;
end if;
y<=cnt;
when “111″=>if(cnt=”0000″)then
cnt<=”1001″;
elsif (cnt=”0101″)then
cnt<=”1001″;
else cnt<=cnt-1;
end if;
y<=cnt;
when others=>cnt<=”1111″;
end case;
end if;
end process;
p2:process(ck)
begin
if(ck’event and ck=’1′)then
case temp is
when 0=>duan<=”000001″;
x<=y;
when 1=>duan<=”000010″;
x<=y;
when 2=>duan<=”000100″;
x<=y;
when 3=>duan<=”001000″;
x<=”0″&sel;
when 4=>duan<=”010000″;
x<=”0″&sel;
when others=>duan<=”100000″;
x<=”0″&sel;
end case;
temp<=temp+1;
end if;
end process p2;
p3:process(x)
begin
case x is
when”0000″=>sm<=”1111110″;
when”0001″=>sm<=”0110000″;
when”0010″=>sm<=”1101101″;
when”0011″=>sm<=”1111001″;
when”0100″=>sm<=”0110011″;
when”0101″=>sm<=”1011011″;
when”0110″=>sm<=”1011111″;
when”0111″=>sm<=”1110000″;
when”1000″=>sm<=”1111111″;
when”1001″=>sm<=”1111011″;
when others=>sm<=”0000000″;
end case;
end process p3;
end art;