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　　DMA and PHUB
　　The PHUB and the DMA controller are responsible for data
　　transfer between the CPU and peripherals, and also data
　　transfers between peripherals. The PHUB and DMA also control
　　device configuration during boot. The PHUB consists of:
　　A central hub that includes the DMA controller, arbiter, and
　　router
　　Multiple spokes that radiate outward from the hub to most
　　peripherals
　　There are two PHUB masters: the CPU and the DMA controller.
　　Both masters may initiate transactions on the bus. The DMA
　　channels can handle peripheral communication without CPU
　　intervention. The arbiter in the central hub determines which
　　DMA channel is the highest priority if there are multiple requests.
　　4.4.1 PHUB Features
　　CPU and DMA controller are both bus masters to the PHUB
　　Eight Multi-layer AHB Bus parallel access paths (spokes) for
　　peripheral access
　　Simultaneous CPU and DMA access to peripherals located on
　　different spokes
　　Simultaneous DMA source and destination burst transactions
　　on different spokes
　　Supports 8, 16, 24, and 32-bit addressing and data